More minor successes

I've been rearranging the VHDL code a lot and it had a positive impact on timing not only in simulation, but on the real hardware, too. The problems with the EPROM 'disappearing' in the middle of the code execution seem to have gone.

Also, I rearranged the assembly code for a (hopefully) more efficient driver. I wrote a test routine that writes a 512 byte block to the card, reads it back and compares the two. The test shows that data is written correctly to the card, but is not read back correctly, sometimes. I think it may have to do with the timing (again) how data is read from the Spi bus into the CPLD. That is about the only thing from the original design, I have not touched. It would surprise me, though, if the was nothing to improve...

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